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DRAC project presentation at the RISC-V & OpenPOWER Workshop
The RISC-V & OpenPOWER Workshop is held in conjunction with the International Conference in Supercomputing, ICS 2020, organized by BSC and UPC as a worldwide online event tihis year.
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Reliability-Aware Memory Design Using Advanced Reconfiguration Mechanisms, November 16, 2015
Located in People / PhD Graduates
Monitor amb control strategies to reduce the impact of Process Variations in digital circuits, December 12, 2015
Located in People / PhD Graduates
DRAC (ERDF) (2019-2023)
Designing RISC-V-based Accelerators for next generation Computers (DRAC) will design, verify, implement and fabricate a high performance general purpose processor that will incorporate different accelerators based on the RISC-V technology, with specific applications in the field of security, genomics and autonomous navigation.
Located in Research / Active research projects
Ultra-low Power Circuits based on Tunnel FETs for Energy Harvesting Applications, May 19, 2017.
Located in People / PhD Graduates
Metodología de diseño lógico redundante para escenarios con ruido extremadamente alto y bajo voltaje de alimentación. January 19, 2016.
Located in People / PhD Graduates
Analysis of the High Frequency Substrate Noise Effects on LC-VCOs. January 29, 2016.
Located in People / PhD Graduates
Investigadors del grup HIPICS participen en el projecte DRAC (Designing RISC-V-based Accelerators for next generation Computers)
DRAC project
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Drac logo
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