Maragda (Spanish MINECO) (2014-2017)

Multilevel approach to the reliability-aware design of analog and digital integrated circuits (Maragda)

Funding entity: Spanish MINECO (Ministerio de Economía)

Period: 2014-2017

Description:

The MARAGDA project is proposed in a context where the manufacturing variability challenge in nanoscale CMOS technologies imposes an important paradigm change in all the aspects related to the IC design. The fabrication processes introduce random atomic-level inhomogeneities, which are observed in the form of device-to-device shifts in the parameters that describe their behavior and performance. In addition, the high electric fields and temperatures in the device, resulting from the aggressive scaling, can trigger aging mechanisms (whose origin should be also found at the nanoscale), which introduce a time dependent drift in the device electrical properties as well. Therefore, the combination of variability and aging leads to a dramatic random and time-dependent variability of the device electrical characteristics, so that nominally identical devices will show statistically distributed performances that change with time. This device-level time-dependent uncertainty will be transferred to circuits and systems, impacting their yield, performance and reliability under conventional design rules.

To fight against the time-dependent variability, as dictated by the ITRS, a multilevel approach has to be adopted, going from the fabrication up to the applications, in which variability and aging effect s are propagated and evaluated, through all the stages of the IC manufacturing process. MARAGDA project adopts such multilevel approach, for the design of high-performance and reliable analog, mixed-signal, RF (AMS/RF) and digital circuits, by coordinating three research teams with complementary expertise in the fields of variability and aging in nanoelectronics: electrical characterization and reliability of devices (UAB), design methodologies for AMS/RF circuits (IMSE-US) and design of AMS/RF (IMSE-US and UPC) and digital (UPC) circuits. Taking advantage of the groups background, the IC design will be addressed by using a multilevel approach, from the nanoscale (where variability and aging have their origin) to circuit/system level (where their effects will be observed), accounting for the interactions between all the abstraction levels.

For ultrascaled devices, variability and aging will be (statistically) studied, using standard (wafer level) and high resolution (n anoscale) characterization techniques, with the aim of proposing device aging models which can be implemented in circuit simulators. These models, together with an efficient reliability-aware circuit simulation methodology (to be developed in the project), will allow the translation of device-level time-dependent variability into statistical circuit performance fluctuation and yield and reliability drop. The resulting simulation methodology will allow the development of new reliability-aware design methodologies, which tackle variability before (preventive techniques) and/or after the circuit fabrication (reactive strategies). New architectural paradigms that explore the benefits that emerging devices could offer to deal with (time-dependent) variability will be also considered. The project includes complete experimental deliverables in all the levels above to validate the investigated concepts and principles.

Partners:

• The Reliability of Electron Devices and Circuits (REDEC) group, from the Universidad Autónoma de Barcelona (UAB) .
• The Research on High Performance Integrated Circuits and Systems (HIPICS) group, from the Universitat Politècnica de Catalunya (UPC).
• The Micro/Nanometric Circuits and Systems (MINCAS) group, from the Instituto de Microelectrónica de Sevilla, IMSE-CNM (CSIC and University of Seville).

Project website:

Maragda website

HIPICS contact person:

Diego Mateo