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Switching and Substrate Noise

Xavier Aragonès, José Luis González, Marc Manel Molina
One of the main obstacles in the implementation of radiocommunication Systems On a single Chip (SoC) in CMOS technology is the noise coupled through the substrate between the parts in the system. Three main needs may be identified by circuit designers to address this problem:
  • Methodologies to predict the substrate noise that affects RF circuits
We have actively worked to identify the sources of substrate noise and mechanisms of coupling. In a journal paper published in JSSC (1999) we identified switching noise in digital power-supply lines connected to substrate taps as the main agent of substrate noise, which has been agreed by works of many other authors. In a later work presented at the 2003 DATE conference and extended in the IEE Proceedings (2003) we identified switching interconnects as a secondary important substrate noise source, and presented a modeling approach verified against experimental measurements. Intensive work on switching noise analysis and modeling and tecniques to reduce its importance was carried out in the 90'ies, resulting in several jounal and conference papers.

We have later worked in developing efficient methodologies to predict substrate noise coming from noisy power-supply lines. Noise is an analog phenomena but obviously a conventional analog simulation of the complete digital section generating the noise is not feasible. Fast-Spice simulators can do a better job in analog simulation of digital circuitry, but they lose efficiency when adding the package models and noise comes into scene. Regarding modeling the substrate itself, there are commercial CAD tools that extract substrate models with reasonable accuracy, but they are generated from a flat layout and result into huge netlists which limit the size of the extracted circuit. To solve this problem, we have implemented a macromodeling methodology for the digital part, i.e. a simple and treatable modeling of the digital part that generated the noise coupled to the substrate. For the substrate, we have proposed a hierarchical extraction model. The details of this methodology, and an evaluation of the speedup and errors made, are contained in Juan Felipe Osorio's PhD Thesis (2011), and a preliminary paper was published in 2004 in Microelectronics Journal.
  • Techniques to avoid or minimize the impact of substrate noise on RF circuits
Understanding how noise propagates depending on the type of substrate and frequency is basic to predict the efficacy of guard rings or other isolation techniques. A compilation of this knowledge was published in the 2003 SPIE conference. We later worked on an experimentally determining the efficacy of decoupling capacitors as noise attenuators, depending on package, frequency, location. We also evaluated noise suppression circuits such as notch filters or feedback. Last, we have been interested in evaluating the efficacy of isolation techniques as noise moves to RF or mmWave frequencies. In 2009 we published in IEEE SOCC Conference a detailed experimental analysis of substrate isolation techniques and the factors that limited their validity.
  • Understand how substrate noise affects the performance of the different building blocs in a RF radio
We first completed a work studying the effect of switching noise on segmented DACs, the experimental results were presented at the 2005 ISCAS conference. Later we focussed on studying how substrate noise affects mixers, VCOs and PLLs, especially the latest two. At the output of a VCO or PLL, noise may appear as continuous phase noise or in the form of sideband spurs, which in both cases are phenomena that may easily provoke violation of a receiver specs. These phenomenas have been extensively studied both analytically and experimentally, using as test vehicles an important number of LC-VCOs (2.4 GHz VCO NMOS and PMOS, 2.4 GHz quadrature VCO; 7 GHz VCO; 57 GHz VCO) and PLL (2.4 GHz), and the results have been extensively published in journals and conferences. Miguel Mendez PhD thesis focussed on low-frequency noise upconversion and impact on VCOs, as well as mixers. Juan Felipe Osorio's PhD thesis focussed on low-frequency noise upconversion and impact on the different blocks of a frequency synthesizer and how these noise sources are shaped when the PLL loop closes, as well as its analytical prediction. Marc Molina's PhD thesis focuses on explaining the spurs observed in a VCO due to RF noise, modeling and determining the factors that set the importance of this phenomena.

Students involved in this area: