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Xavier Aragones

Xavier Aragones

Xavier Aragones Cervera
Associate Professor

M.S. in Telecom Engineering, Universitat Politècnica de Catalunya, 1993 
Ph.D., Electronic Engineering Dept., Universitat Politècnica de Catalunya, 1997

Edifici C4, Campus Nord 
C/ Jordi Girona, 1-3 
ES-08034 Barcelona - Spain 
+34 934017482 (office) 
+34 934016756 (fax) 
xavier.aragones@upc.edu
LinkedIn logo profile: http://www.linkedin.com/pub/xavier-aragones/31/2b6/95/en

Research activities

The increasing speed of digital CMOS circuitry and the high levels of integration achieved make electrical couplings from noisy parts to other sensitive parts in the same IC, especially RF sections, a major and critical problem. The parts involved may be coupled through the inteconnect lines (capacitively), through the common silicon substrate, or through the power-supply lines (SSN). The advent of SoC circuits in which parts generating tones in the range of several GHz co-exist with highly sensitive circuits are worsing the problem, particularly concerning the coupling thorugh the common substrate. Analysis and modeling of these phenomena, proposal of solutions, and the design of circuits challenged by these problems has been my main research area. During the last years we have focussed on analysis and modeling of the effects of substrate noise on VCOs and PLLs, and techniques to reduce the spurs created by this problem. Find out more ...

Students

Publications

You can access the full research records in the UPC Futur website.
You can also visit the HIPICS e-prints page.